Soft error rate estimation for Combinational Logic in Presence of Single Event Multiple Transients

Fast and accurate estimation of soft error rate in VLSI circuits is an essential step in a soft error tolerant ASIC design. In order to have a cost e®ective protection against radiation e®ects in combinational logics, an accurate and fast method for identi ̄cation of most susceptive gates and paths is needed. In this paper, an e±cient, fast and accurate method for soft error propagation probability (SEPP) estimation is presented and its performance is evaluated. This method takes into account all three masking factors in multi cycles. It also considers multiple event transients as a new challenge in soft error tolerant VLSI circuit design. Compared with Monte Carlo (MC) simulation-based fault injection method, our SEPP estimation method has a high level of accuracy (with less than 2% di®erence) while o®ering 1000 speedup as compared with MC-based simulation.